Integrated circuit cell sets are used as building blocks in the design for a wide variety of integrated circuit devices. As an example, U.S. Pat. No. 5,801,407 describes a conventional analog cell that is configured as an operational amplifier that is used to design an integrated circuit. A conventional operational amplifier laid out in a cell arrangement is disclosed in U.S. Pat. No. 6,590,448. This conventional operational amplifier consists of the layout of operational amplifier cells that can be combined to create a larger operational amplifier but due to internal node saturation problem, it has been difficult and impractical to construct larger operational amplifiers. The '448 Patent describes how to combine operational amplifier cells in single, two, and three stage designs and to change Gm.
Conventional analog design methods include designing circuits using a high-level description language, followed by schematic entry and simulating with a variety of simulators with ideal models. The physical layers are then laid out using a layout editor, verified correct using a design rule (DRC) checker, and a layout versus schematic (LVS) checker verifies the layout matches the schematic, verified for electrical rules, power density, temperature density, and then extracted and simulated again.
For example, a conventional design flow may be as follows:                1. Top Level Modeling and Specification        2. Schematic Entry        3. Schematic Level Simulation (pre-extracted circuit)        4. Physical Layout        5. Design Rule verification of Physical Layout (DRC)        6. Physical Layout verification of Schematic (LVS)        7. Verify Electronic Rules (ERC)        8. Extracted circuit from Physical Layout        9. Simulation of extracted circuit        10. Insert Design For Manufacturing Elements        11. Extracted circuit from Physical Layout with Design for Manufacturing elements        12. Simulation of extracted circuit with Design for Manufacturing elements        13. Send Verified circuit to manufacturing plant        
Any errors in the design at any step require repeating the step or going back to previous steps. Due to the complexity of today's designs and manufacturing, many people work together designing a semiconductor circuit and often a different person is assigned to each step.
In addition, during the conventional design process, circuit elements may be used in a variety of complex arrangements. For example, an operational amplifier may be arranged in various parallel arrangements that allows the designer to change the input Gm, internal topology, and output Gm to build circuits that can output large current loads for power applications. Another use of high performance operational amplifiers is in the use of accurate low gain, high bandwidth devices. An issue with the design of analog circuits is that the changing of one transistor or wire in the design affects more than one parameter, which makes the design complicated due to the multivariable changes. For example, when the bandwidth of an operational amplifier must be changed, the designer often finds the Gm is also changed.
Due to the high cost of non-recurring engineering (NRE) for state-of-the-art microelectronics, costs of the design are now exceeding $100M. Much of this cost is due to the mask costs, which itself can exceed $10M. This assumes the chip works the first time which is an increasingly rare occurrence. Each time the chip fails, another mask set may be needed with a cost of another $10M. Large volume chip producers may be able to recoup this amount; however, small volume producers may be cost prohibitive.